1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a synchronous dynamic random access semiconductor memory device (SDRAM device) capable of operating in synchronism with an external clock. More specifically, the present invention is concerned with a refresh operation of such an SDRAM device.
2. Description of the Related Art
Various types of semiconductor memory devices, such as SRAM and DRAM devices have been proposed and have been selectively used in terms of applications and so on. A recent advance of application programs and systems requires a large number of DRAM devices. Under the above situation, SDRAM devices have been attracted because the SDRAM devices can operate in synchronism with a very high-speed external clock.
The SDRAM devices require refresh operations as in the case of general-purpose DRAM devices. Recent DRAM devices are equipped with a plurality of refresh modes such as an automatic refresh (auto-refresh) mode and a self-refresh mode. In the auto-refresh mode, an external clock and an external address are needed to perform the auto-refresh operation. The self-refresh mode does not require the external clock and the external address. In the self-refresh mode, it is possible to hold data in a system standby state without any external signals.
The general-purpose DRAM devices have a mode selecting operation in which given signals such as a column address strobe signal (/CAS) and a row address strobe signal (/RAS) are controlled at given timings. The above operation is called a command entry. For example, a CAS-before-RAS command entries the auto-refresh mode. The self-refresh mode can be entered by holding the /CAS signal during a given time after the CAS-before-RAS command. It should be noted that the symbol "/" denotes a low-active signal.
In the SDRAM devices, the auto-refresh mode and the self-refresh mode can be entered by controlling a clock enable signal CKE, a chip select signal /CS, a write enable signal /WE, the /CAS signal and /RAS signal. The clock enable signal CKE is used to make a decision as to whether an external synchronizing clock signal CLK should be received. For example, the auto-refresh mode can be entered when the clock enable signal CKE is at a high (H) level for two consecutive cycles and when /CS=/RAS=/CAS=L (low level) and /WE=H. Further, when /CS=/RAS /CAS=L and /WE=H at the time of a change of the clock enable signal CKE from H to L, the self-refresh mode can be entered. In the SDRAM device which is in the self-refresh mode, it is possible to stop the control thereof from an external device at any time by input a command synchronized with the clock signal. The command is interpreted by a command decoder built in the DRAM device.
However, the entry of the self-refresh mode in the SDRAM devices has the following disadvantages.
Generally, a system such as a computer, or a peripheral device uses a group of SDRAM devices. Such a group is called a chip set. Each of the DRAMs in the chip set requires the respective chip select signal /CS, low address strobe signal /RAS, column address strobe signal /CAS and write enable signal /WE. That is, these signals are respectively generated for each of the SDRAM devices in the chip set. On the other hand, the clock enable signal CKE used to determine whether the synchronizing clock signal CLK should be received is used common to the SDRAM devices of the chip set. Hence, the clock enable signal CKE has a very heavy load, as compared with the signals /CS, /RAS, /CAS and /WE. The difference between the load burdened by the clock enable signal CKE and the loads burdened by the other signals causes a timing error between the signals. More particularly, a change of the clock enable signal CKE lags behind the changes of the other signals. The timing error affects the command entry operation, particularly entry of the self-refresh mode.
The above timing error makes it impossible to detect the command for entry of the self-refresh mode of the SDRAM device (detect the situation in which /CS=/RAS=/CAS=L and /WE=H at the time when the clock enable signal CKE changes from H to L). In other words, the command entry of the self-refresh mode in the SDRAM device is defined, but cannot be substantially carried out under the situation in which a plurality of SDRAM devices are grouped as a chip set.